Circuits that are sensitive to noise typically use regulated and filtered voltage supplies, since the timing of these circuits can be affected by noise. The effect on timing is especially acute as data rates increase. For example, transceiver timing is extremely critical at high data rates and a transceiver clocking path can have noise sensitivity as high as 4 ps/mV with a corresponding bit period of less than 40 ps. If the clock supply voltage is higher than the data supply voltage, the clock path will be faster than expected which could possibly violate a hold time requirement.